Carnegie Mellon University (CMU) researchers are launching radiation-hardened chip prototypes on a CubeSat in 2026. The project addresses the fundamental problem preventing advanced computing in space: commercial processors fail in radiation environments.

This is not a theoretical study. It is hardware going to orbit for operational testing.

The Radiation Problem

Space radiation destroys electronics. Cosmic rays, solar particle events, and trapped radiation belts bombard satellites with high-energy particles. These particles cause three types of damage:

Single-event upsets (SEU): A particle strike flips a bit in memory or a logic gate, corrupting data or causing incorrect calculations. Temporary, but frequent.

Single-event latchup (SEL): A particle strike creates a high-current path in a transistor, potentially destroying the chip. Permanent damage.

Total ionizing dose (TID): Cumulative radiation exposure degrades transistor performance over time, eventually causing failure. Permanent, progressive damage.

Commercial processors designed for terrestrial use fail rapidly in space. Radiation-hardened processors use specialized manufacturing processes and design techniques to survive, but they lag commercial technology by 10-20 years. Current space-rated processors operate at performance levels equivalent to consumer chips from the early 2000s.

The performance gap is approximately 170,000x. A modern commercial processor delivers 170,000 times more operations per watt than a radiation-hardened space processor.

This gap makes orbital computing impractical for AI workloads, neuromorphic processing, or any application requiring high computational density.

CMU’s Approach: Compact Radiation-Hardened Designs

CMU’s team focused on reducing the chip area required for radiation tolerance. Traditional radiation-hardening techniques use redundancy: triple modular redundancy (TMR) runs three copies of every circuit and votes on the correct output. This triples chip area, increases power consumption, and raises manufacturing costs.

CMU developed compact radiation-hardened flip-flops (data storage elements particularly vulnerable to radiation) that achieve equivalent or superior radiation tolerance compared to conventional designs but with smaller chip area. Smaller area means:

• Lower manufacturing costs: Less silicon per chip
• Higher performance: Shorter signal paths reduce latency
• Improved energy efficiency: Less capacitance to charge and discharge

The team is building full system-on-a-chip prototypes for deployment on a CubeSat in 2026 through a collaborative spacecraft design and construction course.

Technology Readiness Level: TRL 4-5 (laboratory validated, orbital test planned)

Neuromorphic Processors in Space

Neuromorphic processors, which emulate brain-like spiking neural networks, are particularly promising for space applications. They offer high computational efficiency for specific tasks like image analysis, pattern recognition, and autonomous rover control.

However, neuromorphic processors have not been extensively tested for radiation tolerance. Research is underway to characterize their behavior in space environments. The Mentium neuromorphic chip is being investigated for radiation tolerance to enable deployment on various space missions.

Neuromorphic architectures may have inherent radiation advantages. Event-driven processing means most transistors are inactive most of the time, reducing the probability of particle strikes affecting active computations. Sparse, distributed representations may also provide natural error tolerance.

These are hypotheses. The 2026 CubeSat test will provide real data.

22nm FinFET for Space

CMU’s work aligns with broader efforts to bring advanced manufacturing nodes to space-rated processors. NASA is pursuing radiation-tolerant standard cell libraries in GlobalFoundries 22nm FDSOI CMOS fabrication process, with projects underway by companies like Alphacore.

22nm FinFET technology has been demonstrated for space applications, including a 15-22 GHz phase-locked loop (PLL) designed with techniques to mitigate SEU and TID effects. FinFET transistors use a three-dimensional gate structure that provides better control over current flow, reducing leakage and improving radiation tolerance compared to planar transistors.

Moving from 180nm (typical for current space processors) to 22nm provides:

• 8x transistor density: More computing per chip area
• 3-5x performance improvement: Higher clock speeds and lower latency
• 2-3x energy efficiency: Lower voltage operation

This does not close the 170,000x gap, but it narrows it significantly.

The 2026 CubeSat Test

The CubeSat deployment will validate CMU’s compact radiation-hardened designs in the actual space environment. Laboratory radiation testing simulates space conditions, but real orbital exposure provides data on:

• Long-duration TID effects: Months to years of cumulative radiation damage
• SEU rates in real radiation belts: Particle flux varies with orbit and solar activity
• Thermal cycling stress: Temperature swings between sunlight and shadow
• Combined effects: Radiation, thermal, and vacuum stresses interact in ways difficult to simulate

If the 2026 test succeeds, it demonstrates that compact radiation-hardened designs can survive in orbit while providing better performance and lower cost than traditional approaches.

If it fails, it provides data on failure modes and informs the next design iteration.

Either outcome advances the field.

Implications for Orbital Computing

Radiation-hardened processors are the bottleneck for orbital computing. China’s Three-Body Computing Constellation, SpaceX’s proposed orbital data centers, and speculative projects like ArkSpace’s exocortex constellation all require processors that can survive space radiation while delivering high performance.

CMU’s work, NASA’s 22nm FDSOI program, and neuromorphic radiation tolerance research collectively address this bottleneck. The 2026 CubeSat test is one data point in a broader effort to close the 170,000x performance gap.

The timeline for practical orbital computing depends on how quickly radiation-hardened processors can approach commercial performance levels. If 22nm FinFET succeeds in space, 14nm and 7nm nodes may follow within a decade.

At that point, orbital computing becomes economically viable, not just technically possible.

Official Sources

1. Carnegie Mellon University: Compact Radiation-Hardened Chip Design
2. Carnegie Mellon ECE: 2026 CubeSat Deployment Plans
3. NASA: Neuromorphic Processors for Space Applications
4. NASA: Radiation Tolerance of Neuromorphic Chips
5. NASA: Mentium Neuromorphic Chip Radiation Testing
6. NASA: 22nm FDSOI Radiation-Tolerant Standard Cell Libraries
7. IEEE: Radiation-Hardened 22nm FinFET Phase-Locked Loop Design
8. arXiv: Radiation Hardening Techniques for Advanced CMOS Nodes